1. Technical Field
A method for forming a transistor of a semiconductor device is disclosed and, in particular, an improved method for forming a metal-oxide-semiconductor field effect transistor (MOSFET) or metal-insulator-semiconductor field effect transistor (MISFET) is disclosed which has an ultra-shallow super-steep-retrograde epitaxial channel with a channel length below 100 nm that can be applied to an ultra large scale integrated (ULSI) semiconductor device.
2. Description of the Related Art
A surface region below a gate electrode and a gate insulating film of a MOSFET or MISFET semiconductor device serves as a current path when an electric field is applied to a source/drain region with a voltage applied to a gate. This region is called a channel.
The characteristics of the MOSFET or MISFET semiconductor device are determined by a dopant concentration in the channel region. Specifically, the characteristics of the device such as a threshold voltage of a transistor and a drain current are dependent upon the dopant concentration, and thus the channel region must be precisely doped.
Conventional channel doping methods include well ion implantation, channel ion implantation, threshold voltage ion implantation, and other related techniques.
According to the aforementioned methods, a flat channel having a constant channel region concentration in a depthwise direction, a buried channel formed in a specific channel depth, and a retrograde channel having a channel concentration which increases in a depthwise direction can be formed.
A channel structure for a high performance microprocessor having a channel length less than 0.2 xcexcm is a retrograde channel which is formed according to heavy ion implantation using In, As and Sb. Here, a surface dopant concentration Cs is low so that surface mobility is improved. It is thus possible to manufacture a high performance MOSFET having a good current driving characteristics.
A channel depth Wd must be decreased as a channel length is reduced. Accordingly, the retrograde channel having a channel depth of less than 50 nm cannot be formed via only the ion implantation.
An epitaxial channel has been suggested to solve the foregoing problem. However, since loss and diffusion of channel dopants during an epitaxial channel formation and subsequent thermal process are difficult to control, conventional epitaxial channel transistors fail to provide an improved Ion/Ioff characteristics.
The most idealistic channel doping method is to embody a xcex4-doped epitaxial channel. However, an embodyment of a xcex4-doped epitaxial channel having a channel depth of less than 30 nm has not been reported to be possible diffusion of dopants in the subsequent process even when a doped epitaxial layer and an undoped epitaxial layer are employed.
A method for preventing diffusion of a xcex4-doped layer by doping a channel according to ultra-low energy ion implantation and then instantaneously performing laser thermal process thereon has been suggested at IEDM 2000 by, Lee Jungho, Lee Jungyeop et al., in xe2x80x98Laser Thermal Annealed SSR Well prior to epitaxial channel Growth (LASPE) for 70 nm nFETxe2x80x99. It has been reported that the laser thermal process controls loss and diffusion dopants during selective epitaxial growth (SEG).
However, the laser thermal process, which controls loss and diffusion of dopants to the epitaxial layer, generates partial melting on a silicon substrate under the laser power, resulting in an aggravation of surface roughness of the substrate and a generation of crystal defect, and cannot be applied to a practical method for manufacturing a semiconductor device.
Accordingly, a method for forming a transistor of a semiconductor device is disclosed which provides high integration density of the semiconductor device by controlling loss of dopants during thermal process and diffusion of dopant during SEG
In order to achieve the above-described object of the invention, a method for forming a transistor of a semiconductor device is disclosed which comprises: (a) defining a first and a second regions on a semiconductor substrate using a device isolation pattern; (b) ion-implanting a first conductive type impurity into the first region to form a first channel layer; (c) ion-implanting a second conductive type impurity into the second region, using exposure mask to form a second channel layer; (d) performing high temperature thermal process to stabilize the first and second channel layers; (e) performing a hydrogen treatment process on the structure resulting from step (d); (f) growing undoped silicon epitaxial layers on the first and the second channel layers of the first conductive type and the stabilized channel layer whereby generating a first and a second xcex4-doped epitaxial channels of a super-steep-retrograde structure; (g) forming a gate insulating film and a gate electrode on the first and the second xcex4-doped epitaxial channels, respectively; (h) re-oxidizing the gate insulating film to repair damaged portions of the gate insulating film; and (i) forming a source/drain region and performing a low temperature thermal process.
The ion-implanting process into the first region is performed using As ions at an ion implantation energy ranging from 3 to 30 KeV, or P ions at an ion implantation energy ranging from 1 to 15 KeV; the first channel layer is formed at a depth ranging from 10 to 50 nm below the surface of the semiconductor substrate; the ion-implanting process into the second region is performed using B ions at an ion implantation energy ranging from 100 eV to 1.5 KeV; the second channel layer is formed at a depth ranging from 10 to 50 nm below the surface of the semiconductor substrate; the high temperature thermal process is a rapid thermal process performed at a temperature ranging from 900 to 1000xc2x0 C.; the step of performing a high temperature thermal process is a spike rapid thermal process performed at a temperature ranging from 1000 to 1100xc2x0 C.; the undoped silicon epitaxial layers has a thickness ranging from 50 to 30 nm; the step of forming a gate insulating film is performed by growing a low temperature thermal oxide film under steam atmosphere at a temperature ranging from 650 to 750xc2x0 C.; the step of forming a gate insulating film comprises forming a low temperature thermal oxide film and nitriding the low temperature thermal oxide film with plasma treatment to form a low temperature oxide-nitride film; the gate insulating film is a low-temperature high-dielectric film; the step of forming a gate insulating film comprises depositing a low-temperature high-dielectric film at a temperature ranging from 300 to 650xc2x0 C. and performing a thermal annealing process in a furnace at a temperature ranging from 400 to 700xc2x0 C.; the step of forming a gate insulating film comprises depositing a low-temperature high-dielectric film at a temperature ranging from 300 to 650xc2x0 C. and performing a rapid thermal annealing process at a temperature ranging from 600 to 800xc2x0 C.; the step of forming a gate insulating film comprises growing a low temperature thermal oxide film under steam atmosphere at a temperature ranging from 650 to 700xc2x0 C.; depositing a high-dielectric material on the low temperature thermal oxide film at a temperature ranging from 300 to 650xc2x0 C.; and performing a thermal annealing process in a furnace at a temperature ranging from 400 to 700xc2x0 C.; the step of forming a gate insulating film comprises growing a low temperature thermal oxide film under steam atmosphere at a temperature ranging from 650 to 750xc2x0 C.; depositing a high-dielectric material on the low temperature thermal oxide film at a temperature ranging from 300 to 650xc2x0 C.; and performing a rapid thermal annealing process at a temperature ranging from 600 to 800xc2x0 C.; the step of re-oxidizing gate insulation films is performed by a rapid thermal oxidation process at a temperature ranging from 750 to 950xc2x0 C.; the step of re-oxidizing gate insulation films is performed by a rapid spike thermal oxidation process at a temperature ranging from 600 to 1100xc2x0 C.; the step (h) is processed by a thermal oxidation process performed in an oxidation furnace at a temperature ranging from 650 to 800xc2x0 C.; the low temperature thermal process of step (i) is performed by a rapid thermal annealing process at a temperature ranging from 600 to 1000xc2x0 C.; the low temperature thermal process of step (i) is performed by a rapid spike thermal annealing process at a temperature ranging from 600 to 1100xc2x0 C.; the low temperature thermal process of step (i) is performed in a furnace at a temperature ranging from 300 to 750xc2x0 C.
An ultra-shallow super-steep-retrograde epitaxial channel having a channel depth ranging from 10 to 30 nm is formed by controlling loss of dopants during subsequent hydrogen prebake process prior to SEG and diffusion of dopants during SEG by performing ion implantation for doping channel using a low ion implantation energy, and performing high temperature rapid thermal process at a temperature below a silicon melting point.